Lossless planar chip inductance test assembly and manufacturing method thereof

The invention discloses a lossless planar chip inductance testing assembly and a manufacturing method thereof, and belongs to the field of electronic component testing. The test assembly comprises a base, an embedded part and a calibration part. The base comprises a base substrate, a positioning cavity and a base electrode; the embedded part comprises an embedded part substrate, a through hole, a through hole metallization filler, an embedded part bottom electrode, an embedded part surface electrode and an embedded part end electrode; the calibration piece comprises a calibration piece substrate, a calibration piece through hole, a calibration piece through hole metallization filler, a calibration piece bottom electrode, a calibration piece surface electrode, a calibration piece end electrode and a calibration piece electrode connecting wire; the shape, the structure and the size of the calibration piece are consistent with those of the embedded piece, and the difference is that a calibration piece electrode