SENSING CIRCUIT FOR SENSING TWO STATES OF MEMORY CELL

The invention relates to a sensing circuit for sensing two states of a memory cell. An apparatus includes a memory array and a sensing circuit coupled with the memory array. The sensing circuitry includes a sensing node coupled with a data line of the memory array. A first sense path includes a first transistor having a first gate coupled with the sense node. A second sense path includes a second transistor having a second gate coupled with the sense node. A first threshold voltage of the first transistor differs from a second threshold voltage of the second transistor by a threshold voltage gap. 本申请涉及用于感测存储器单元的两种状态的感测电路。一种装置包含存储器阵列和与所述存储器阵列耦合的感测电路。所述感测电路包含与所述存储器阵列的数据线耦合的感测节点。第一感测路径包含具有与所述感测节点耦合的第一栅极的第一晶体管。第二感测路径包含具有与所述感测节点耦合的第二栅极的第二晶体管。所述第一晶体管的第一阈值电压与所述第二晶体管的第二阈值电压相差阈值电压间隙。