Simulation circuit reliability simulation method based on dynamic step length

The invention discloses an analog circuit reliability simulation method based on dynamic step length, and mainly solves the problems that the prior art cannot fit the actual degradation condition of a device, and the simulation precision and speed cannot be considered at the same time. According to the implementation scheme, the method comprises the following steps: reading set degradation time T and s step lengths from a circuit simulation input file; calculating initial step length time t0 = T/s, and assigning the initial step length time t0 to each step length; inputting a device degradation model function, and calculating a degradation rate function f (t) along with time; performing scaling calculation on s step lengths with values of t0 through degradation rates f (t) of a device degradation function at different moments to obtain a group of dynamic step lengths; and performing circuit reliability simulation by using the dynamic step length to obtain a degradation result of the circuit characteristic ind