Neural network accelerator automation code generation method

The invention discloses an automatic code generation method for a neural network accelerator. According to the method, automatic code generation of the high-performance FPGA accelerator can be realized. Firstly, on the hardware level, convolution operation is mapped into general matrix multiplication (GEMM), and then appropriate hardware design parameters are selected for each layer so as to realize the neural network accelerator with high calculation efficiency. On the software level, a compiler analyzes the ONNX model to obtain a neural network model structure, operators which can be realized on FPGA hardware are finally mapped through a series of operation such as operator fusion, and finally code generation of the whole accelerator is realized through cascading of the operators. Meanwhile, the compiler can optimize hardware resources by adjusting hardware design parameters. 本发明公开一种神经网络加速器自动化代码生成方法。该方法可实现高性能FPGA加速器的自动化代码生成。首先在硬件层面，通过对卷积操作映射成通用矩阵乘法(GEMM)，之后为每层选取合适的硬件设计参数以实现高计算效率的神经网络加速器。在软件层面，编译器解析ONNX模型以获得