Hardware accelerator of convolutional spiking neural network based on STDP online learning

The invention discloses a hardware accelerator of a convolutional spiking neural network based on STDP online learning, which adopts two algorithms of STDP and RSTDP to combine for training, supports online learning of the network, and can adapt to a dynamically changing environment. The hardware accelerator is composed of an upper computer and an FPGA, the upper computer carries out data preprocessing such as pulse coding, and the FPGA carries out actual network calculation. The accelerator is realized on an FPGA (Field Programmable Gate Array) of a ZCU102 model of Xilinx, and is finally trained on an MNIST data set, and the test accuracy can reach 95%. The method supports small sample learning, and even if the quantity with labels is reduced to 20% of that of an original training set, the test accuracy can still reach about 95%. Under the clock frequency of 100 MHz, the reasoning time of each image is 0.16 s, the training time is 0.177 s, and the processing speed is improved by 16 times compared with that o