Effective method for VLSI (Very Large Scale Integration) implementation of useful neural network activation function
A neural inference chip is provided that includes at least one neural inference core. The at least one neuro-inference core is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of intermediate outputs. The at least one neural inference core i...
Gespeichert in:
Hauptverfasser: | , , , , , , , , , , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | A neural inference chip is provided that includes at least one neural inference core. The at least one neuro-inference core is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of intermediate outputs. The at least one neural inference core includes a plurality of activation units configured to receive the plurality of intermediate outputs and generate a plurality of activations. Each of the plurality of activation units is configured to apply a configurable activation function to its input. The configurable activation function has at least a re-varying range term and a scaling term, the re-varying range term determining a range of the activation and the scaling term determining a scaling of the activation. Each of the plurality of activation units is configured to obtain the re-variation range item and the scaling item from one or more lookup tables.
提供了一种神经推理芯片,包括至少一个神经推理核心。该至少一个神经推理核心适于将多个突触权重应用于多个输入激活以产生多个中间输出。所述至少一个神经推理核心包括多个激活单元,所述多个激活单元被配置为接收所述多 |
---|