Latch architecture and latch circuit

The invention discloses a latch architecture and a latch circuit. The latch architecture includes an input circuit that receives input data; a combination network providing first intermediate data, a first intermediate control signal, and a second intermediate control signal based on latched input data from the input circuit; one or more first latches that provide latched first intermediate data; a second latch which provides a latched first intermediate control signal; a third latch which provides a latched second intermediate control signal; at least one fourth latch providing output data; the decoder is connected to the first latch, receives the latched first intermediate data and provides second intermediate data. At least one fourth latch receives an input signal modified based on the latched first intermediate control signal, the latched second intermediate control signal, and the second intermediate data. The first to third latches operate with an inverted clock signal, and the at least one fourth latc