Arsenic diffusion profile construction method for transistor

Embodiments of the present disclosure relate to methods for forming source/drain extensions. In one embodiment, a method for forming an nMOS device includes forming a gate electrode and a gate spacer on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to expose sidewalls and a bottom, forming an arsenic doped silicon (Si: As) layer on the sidewalls and the bottom, and forming a source/drain region on the Si: As layer. During deposition of the Si: As layer and formation of the source/drain region, an arsenic dopant is diffused from the Si: As layer into a third portion of the semiconductor fin positioned below the gate spacer, and the third portion becomes a doped source/drain extension region. By utilizing the Si: As layer, doping of the source/drain extension region is controlled, resulting in reduced contact resistance while reducing dopant diffusion into the channel region. 本公开案的实施方式关于用于形成源极/漏极延伸的方法。在一个实施方式中，一种用于形成nMOS装置的方法包括以下步骤：在半导体鳍片的第一部分上形成栅极电极与栅极隔件，移除半导体鳍片的第二部