Stacked chip package

A stacked chip package of the inventive concept includes a first chip and a second chip stacked on the first chip. The first chip may include a first cell array region, a first core circuit region including a first core terminal, and a first peripheral circuit region including a plurality of first peripheral circuit terminals. The second chip may include: a second cell array region on the first cell array region; a second core circuit region on the first core circuit region and including a second core terminal; and a through hole on the first peripheral circuit region and connected to at least one first peripheral circuit terminal of the plurality of first peripheral circuit terminals. 一种本发明构思的堆叠芯片封装包括：第一芯片和堆叠在所述第一芯片上的第二芯片。所述第一芯片可以包括第一单元阵列区、包括第一核心端子的第一核心电路区、以及包括多个第一外围电路端子的第一外围电路区。所述第二芯片可以包括：第二单元阵列区，在所述第一单元阵列区上；第二核心电路区，在所述第一核心电路区上并包括第二核心端子；以及贯通孔，在所述第一外围电路区上并连接到所述多个第一外围电路端子中的至少一个第一外围电路端子。