Digital processing circuit

The invention discloses a digital processing circuit, comprising a logic unit comprising at least one combinational logic device, the combinational logic device comprising at least one input end; and the filtering unit is used for dividing the waveform of the received initial input signal into at least two sections of waveforms in one period of the clock signal of the combinational logic device and preventing burrs contained in at least one section of waveform from spreading backwards so as to provide a filtered input signal to the input end of the combinational logic device. According to the invention, the filtering unit prevents the burrs contained in at least one waveform in the initial input signal from spreading backwards, and can eliminate the influence of the burrs in the signal on the power consumption of the whole circuit in time, thereby effectively reducing the extra power consumption caused by the burrs. 本申请公开了一种数字处理电路，包括逻辑单元，包括至少一个组合逻辑器件，组合逻辑器件包括至少一个输入端；滤波单元，用于在组合逻辑器件的时钟信号的一个周期内将接收的初始输入信号的波形分为至少两