Interface circuit, processor including same, and method of processing packet

An interface circuit, a processor including the interface circuit, and a method of processing a packet are disclosed. The interface circuit includes: a packet transmitter configured to generate a plurality of transport packets based on a request output from a core circuit, and output the plurality of transport packets, the plurality of transport packets including information indicating packets to be merged; and a packet receiver configured to generate a merged packet by merging a plurality of extended packets including information indicating packets to be merged among a plurality of received packets received from outside of the interface circuit. 公开了接口电路、包括接口电路的处理器以及处理包的方法。所述接口电路包括：包发送器，被配置为：基于从核电路输出的请求来生成多个传输包，并且输出所述多个传输包，所述多个传输包包括指示为将被合并的包的信息；以及包接收器，被配置为：通过合并从所述接口电路的外部接收的多个接收包之中的多个扩展包来生成合并包，所述多个扩展包包括指示为将被合并的包的信息。