Single event upset immune trigger using small-area high-resistance element

A SEU immune flip-flop includes a primary data latch transparent in response to a first state of a clock signal and locked in response to a second state of the clock signal; a slave stage data latch; and a scan slave latch having an input coupled to the slave stage data latch scan output, the scan s...

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Bibliographische Detailangaben
Hauptverfasser: JOHNSON, PAUL, ONIMUS DAN, BRITTON BRIAN, SCHADT JOHANNES
Format: Patent
Sprache:chi ; eng
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Zusammenfassung:A SEU immune flip-flop includes a primary data latch transparent in response to a first state of a clock signal and locked in response to a second state of the clock signal; a slave stage data latch; and a scan slave latch having an input coupled to the slave stage data latch scan output, the scan slave latch being transparent in response to the clock signal second state and locked in response to the clock signal first state. The slave level data latch includes a switching inverter that is disabled when the slave latch is in a transparent state and that is enabled when the slave latch is in a locked state having a time delay longer than an SEU period. 一种SEU免疫触发器包括主级数据锁存器,所述主级数据锁存器响应于时钟信号第一状态而透明并且响应于时钟信号第二状态而锁定;从级数据锁存器;以及扫描从锁存器,所述扫描从锁存器具有耦合到所述从级数据锁存器扫描输出的输入,所述扫描从锁存器响应于所述时钟信号第二状态而透明并且响应于所述时钟信号第一状态而锁定。所述从级数据锁存器包括开关反相器,当所述从锁存器处于透明状态时所述开关反相器禁用并且当所述从锁存器处于具有比SEU时间段长的时间延迟的锁定状态时所述开关反相器启用。