Chip stop current test system and method thereof

The invention discloses a chip stop current test system which is characterized in that an instruction filling module is used for being connected with a JTAG (Joint Test Action Group) port of a chip; moreover, after the chip enters a debug mode, the instruction filling module fills an instruction to a CPU (Central Processing Unit) in the chip for execution through the JTAG port; according to the system, the utilization of flash in a chip is avoided. According to the invention, the test time and the comprehensive cost are greatly reduced, and the test efficiency of chip mass production is improved. 本发明揭示了一种芯片stop电流测试的系统，其特征在于：指令灌入模块，用于连接芯片的JTAG口；并且，当芯片进入debug模式后，所述指令灌入模块通过所述JTAG口灌入指令给芯片中的CPU执行；其中，所述系统免除对芯片中flash的利用。本发明极大的减少了测试的时间和综合成本，提高了芯片量产的测试效率。