Trigger unit including clock gating circuit

The invention discloses a trigger unit including a clock gating circuit. The trigger unit comprises an edge trigger and a clock gating circuit, the clock gating circuit enables or shields a first clock signal according to a clock control signal to generate a second clock signal and a third clock signal, the second clock signal and the third clock signal are inverted with each other, the second clock signal provides a trigger edge of the edge trigger, and the third clock signal provides a trigger edge of the edge trigger. The clock gating circuit maintains the second clock signal and the third clock signal at respective predetermined levels at least in a clock period in which the clock control signal is turned from a valid state to an invalid state. A clock gating circuit in the trigger unit provides a second clock signal and a third clock signal which are opposite in phase, so that burrs of the second clock signal and the third clock signal can be eliminated, the number of logic elements of the clock gating c