Method for transmitting data between FPGA (Field Programmable Gate Array) chips during transmission bandwidth mismatch

The invention discloses a method for transmitting data between FPGA chips during transmission bandwidth mismatch. The method comprises the following steps: determining a transmission rate required by AD data; obtaining an actual transmission rate according to the line transmission rate and the coding mode of the high-speed transceiver; solving a sampling clock frequency of a user port; determining the number of transmission lines; determining the number of transmission lines and the least common multiple of AD data bit width, and solving integers P and Q; calculating parameters A, B and C; the AD data obtained through A.Q times of sampling is framed and then sent out through the sending end of the N-channel high-speed transceiver in B.P times; adding 1 to the serial number of the subsequent AD data after the AD data obtained by sampling for A.Q times is sent; each channel prepares to receive AD data from the same serial number, and when receiving the user port clock data of the A.P high-speed transceivers, re