Low latency register error correction

Apparatuses and techniques for low latency register error correction are described herein. A register is read as part of an instruction when the instruction is a currently executing instruction in a processor. A correctable error in data generated by reading the register may be detected. In response to detecting the correctable error, the currently executed instruction in the processor may become a register update instruction that is executed to overwrite the data in the register with corrected data. The original (e.g., unchanged) instructions may then be rescheduled. 本文中描述用于低时延寄存器错误校正的装置和技术。当指令是处理器中的当前执行的指令时作为所述指令的一部分读取寄存器。可检测由读取所述寄存器产生的数据中的可校正错误。响应于检测到所述可校正错误，所述处理器中的所述当前执行的指令可变成寄存器更新指令，所述寄存器更新指令经执行以用经校正数据覆写所述寄存器中的所述数据。接着，可重新调度原始(例如，未改变的)指令。