Method for testing high-resistance failure of semiconductor device
The invention provides a semiconductor device high-resistance failure test method, which comprises the following steps: providing a test sample and a design layout thereof, and setting a path in which high resistance possibly exists in the test sample as a to-be-tested path; finding out two end poin...
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creator | TAKESHIRO GAO JINDE DUAN SHUQING |
description | The invention provides a semiconductor device high-resistance failure test method, which comprises the following steps: providing a test sample and a design layout thereof, and setting a path in which high resistance possibly exists in the test sample as a to-be-tested path; finding out two end points of the to-be-tested path according to the design layout, and connecting the to-be-tested path to a test circuit; and performing an electrical test on the to-be-tested path, and judging whether the to-be-tested path has high resistance or not according to a test result of the electrical test. By setting the to-be-tested path of the semiconductor device and performing the electrical test on the to-be-tested path, whether the high-resistance failure exists in the to-be-tested path or not is accurately judged, and the test efficiency is improved.
本发明提供了一种半导体器件高阻失效的测试方法,包括:提供测试样品及其设计版图,将所述测试样品中可能存在高阻的路径设置为待测路径;根据所述设计版图找到所述待测路径的两个端点,并将所述待测路径接入一测试电路;以及,对所述待测路径进行电性测试,根据所述电性测试的测试结果判断所述待测路径是否存在高阻。本发明通过设置半导体器件的待测路径并对其进行电性测 |
format | Patent |
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本发明提供了一种半导体器件高阻失效的测试方法,包括:提供测试样品及其设计版图,将所述测试样品中可能存在高阻的路径设置为待测路径;根据所述设计版图找到所述待测路径的两个端点,并将所述待测路径接入一测试电路;以及,对所述待测路径进行电性测试,根据所述电性测试的测试结果判断所述待测路径是否存在高阻。本发明通过设置半导体器件的待测路径并对其进行电性测</description><language>chi ; eng</language><subject>MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220415&DB=EPODOC&CC=CN&NR=114355136A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220415&DB=EPODOC&CC=CN&NR=114355136A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TAKESHIRO</creatorcontrib><creatorcontrib>GAO JINDE</creatorcontrib><creatorcontrib>DUAN SHUQING</creatorcontrib><title>Method for testing high-resistance failure of semiconductor device</title><description>The invention provides a semiconductor device high-resistance failure test method, which comprises the following steps: providing a test sample and a design layout thereof, and setting a path in which high resistance possibly exists in the test sample as a to-be-tested path; finding out two end points of the to-be-tested path according to the design layout, and connecting the to-be-tested path to a test circuit; and performing an electrical test on the to-be-tested path, and judging whether the to-be-tested path has high resistance or not according to a test result of the electrical test. By setting the to-be-tested path of the semiconductor device and performing the electrical test on the to-be-tested path, whether the high-resistance failure exists in the to-be-tested path or not is accurately judged, and the test efficiency is improved.
本发明提供了一种半导体器件高阻失效的测试方法,包括:提供测试样品及其设计版图,将所述测试样品中可能存在高阻的路径设置为待测路径;根据所述设计版图找到所述待测路径的两个端点,并将所述待测路径接入一测试电路;以及,对所述待测路径进行电性测试,根据所述电性测试的测试结果判断所述待测路径是否存在高阻。本发明通过设置半导体器件的待测路径并对其进行电性测</description><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyzEOwjAQBVE3FAi4w3KAFFYIPUQgGqjoI8v-jlcKduTdcH4oOADVNG_W5nyHphIolkoKUc4jJR5TUyEs6rIHRcfTUkElkuDFvuSweP0OAW_22JpVdJNg9-vG7K-XZ39rMJcBMjuPDB36h7WHtutsezy1_5gPXXUyUw</recordid><startdate>20220415</startdate><enddate>20220415</enddate><creator>TAKESHIRO</creator><creator>GAO JINDE</creator><creator>DUAN SHUQING</creator><scope>EVB</scope></search><sort><creationdate>20220415</creationdate><title>Method for testing high-resistance failure of semiconductor device</title><author>TAKESHIRO ; GAO JINDE ; DUAN SHUQING</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN114355136A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>TAKESHIRO</creatorcontrib><creatorcontrib>GAO JINDE</creatorcontrib><creatorcontrib>DUAN SHUQING</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TAKESHIRO</au><au>GAO JINDE</au><au>DUAN SHUQING</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for testing high-resistance failure of semiconductor device</title><date>2022-04-15</date><risdate>2022</risdate><abstract>The invention provides a semiconductor device high-resistance failure test method, which comprises the following steps: providing a test sample and a design layout thereof, and setting a path in which high resistance possibly exists in the test sample as a to-be-tested path; finding out two end points of the to-be-tested path according to the design layout, and connecting the to-be-tested path to a test circuit; and performing an electrical test on the to-be-tested path, and judging whether the to-be-tested path has high resistance or not according to a test result of the electrical test. By setting the to-be-tested path of the semiconductor device and performing the electrical test on the to-be-tested path, whether the high-resistance failure exists in the to-be-tested path or not is accurately judged, and the test efficiency is improved.
本发明提供了一种半导体器件高阻失效的测试方法,包括:提供测试样品及其设计版图,将所述测试样品中可能存在高阻的路径设置为待测路径;根据所述设计版图找到所述待测路径的两个端点,并将所述待测路径接入一测试电路;以及,对所述待测路径进行电性测试,根据所述电性测试的测试结果判断所述待测路径是否存在高阻。本发明通过设置半导体器件的待测路径并对其进行电性测</abstract><oa>free_for_read</oa></addata></record> |
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subjects | MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING |
title | Method for testing high-resistance failure of semiconductor device |
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