Layout structure design method of high-precision DCOC

The invention discloses a layout structure design method of a high-precision DCOC, which is characterized in that the overall layout adopts central symmetry distribution, mos transistors of Q paths are distributed in the direction of left upper and right lower diagonals, mos transistors of I paths are distributed in the direction of right upper and left lower diagonals, and dummy mos transistors are distributed on the outermost side of the whole DCOC; dummy mos transistors are distributed in the middle of the layouts on the left side and the right side of the whole layout structure; dummy mos transistors are uniformly distributed on the diagonal lines of the whole layout; and in the layouts on the left side and the right side of the layout, the number of the mos tubes of the multiple current sources in the I path is the same as that of the mos tubes of the multiple current sources in the Q path. According to the frequency divider, a central symmetry matching mode is adopted, signal mismatch caused by the tech