Visual control heterogeneous soc chip architecture based on RISC-V

The invention discloses a visual control heterogeneous soc (Soc) chip architecture based on RISC-V. The visual control heterogeneous soc chip architecture comprises a core processor, a digital signal processing unit, an interface circuit and a reset clock control module which are integrated and interconnected through a bus, the core processor adopts a four-core CPU (Central Processing Unit) of an RISC-V architecture and has a modularized organization form and less than hundreds of instructions; the digital signal processing unit is provided with at least one 64-bit dual-core DSP (Digital Signal Processor), and the interface circuit is divided into a communication circuit, a lower computer control circuit and a storage control circuit according to functions, is connected with peripheral equipment and is used for data storage and peripheral equipment control. According to the chip architecture, the advantages of exquisite architecture and simple instruction of the CPU are fully utilized, and the flexibility of