Clock delay test method and clock delay test system

The invention provides a clock delay test method which comprises the following steps: instantiating a phase-locked loop unit and a trigger unit, sending a first clock and a second clock by the phase-locked loop unit, so that the first clock is transmitted along a global clock tree and is transmitted to a data end of the trigger unit through an interconnection unit, transmitting the second clock to a sampling end of the trigger unit along a global clock tree, calculating a first delay of the first clock transmitted in the global clock tree and a second delay of the second clock transmitted in the global clock tree, and adjusting the phase shift of the second clock so that the second clock lags behind the first clock, according to the method, the first delay time of the second clock lags behind the first clock until the output of the trigger unit jumps, the delay time of the second clock lagging behind the first clock is obtained, and the delay clock between the clock regions is calculated according to the firs