In-chip interference test method and in-chip interference test system

In-chip interference test method and in-chip interference test system

The invention provides a method for testing interference in a chip, which comprises the following steps of: establishing a testing environment, connecting an input end of a first low-noise amplifier to a first end of a first component, and connecting an output end of the first low-noise amplifier to...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: GUO JIASHUAI, DENG LIULEI
Format: Patent
Sprache:chi ; eng
Schlagworte:
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator GUO JIASHUAI
DENG LIULEI
description The invention provides a method for testing interference in a chip, which comprises the following steps of: establishing a testing environment, connecting an input end of a first low-noise amplifier to a first end of a first component, and connecting an output end of the first low-noise amplifier to a second detection channel port of a vector network analyzer; the input end of a second low-noise amplifier is connected to a first detection channel port of the vector network analyzer, and the output end of the second low-noise amplifier is connected to the first end of another second component; the signal control output end of the control equipment is connected to the signal control input end of the chip to be tested; power is supplied and work is started; an interference waveform image is obtained, the first low-noise amplifier and the second low-noise amplifier are turned on at the same time through the control equipment, and the S21 parameter waveform is displayed on the vector network analyzer. The embodime
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN114264935A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN114264935A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN114264935A3</originalsourceid><addsrcrecordid>eNrjZHD1zNNNzsgsUMjMK0ktSkstSs1LTlUoSS0uUchNLcnIT1FIzEsBSuJSVFxZXJKay8PAmpaYU5zKC6W5GRTdXEOcPXRTC_LjU4sLEpNT81JL4p39DA1NjMxMLI1NHY2JUQMA5JwzLw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>In-chip interference test method and in-chip interference test system</title><source>esp@cenet</source><creator>GUO JIASHUAI ; DENG LIULEI</creator><creatorcontrib>GUO JIASHUAI ; DENG LIULEI</creatorcontrib><description>The invention provides a method for testing interference in a chip, which comprises the following steps of: establishing a testing environment, connecting an input end of a first low-noise amplifier to a first end of a first component, and connecting an output end of the first low-noise amplifier to a second detection channel port of a vector network analyzer; the input end of a second low-noise amplifier is connected to a first detection channel port of the vector network analyzer, and the output end of the second low-noise amplifier is connected to the first end of another second component; the signal control output end of the control equipment is connected to the signal control input end of the chip to be tested; power is supplied and work is started; an interference waveform image is obtained, the first low-noise amplifier and the second low-noise amplifier are turned on at the same time through the control equipment, and the S21 parameter waveform is displayed on the vector network analyzer. The embodime</description><language>chi ; eng</language><subject>MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220401&amp;DB=EPODOC&amp;CC=CN&amp;NR=114264935A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220401&amp;DB=EPODOC&amp;CC=CN&amp;NR=114264935A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GUO JIASHUAI</creatorcontrib><creatorcontrib>DENG LIULEI</creatorcontrib><title>In-chip interference test method and in-chip interference test system</title><description>The invention provides a method for testing interference in a chip, which comprises the following steps of: establishing a testing environment, connecting an input end of a first low-noise amplifier to a first end of a first component, and connecting an output end of the first low-noise amplifier to a second detection channel port of a vector network analyzer; the input end of a second low-noise amplifier is connected to a first detection channel port of the vector network analyzer, and the output end of the second low-noise amplifier is connected to the first end of another second component; the signal control output end of the control equipment is connected to the signal control input end of the chip to be tested; power is supplied and work is started; an interference waveform image is obtained, the first low-noise amplifier and the second low-noise amplifier are turned on at the same time through the control equipment, and the S21 parameter waveform is displayed on the vector network analyzer. The embodime</description><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHD1zNNNzsgsUMjMK0ktSkstSs1LTlUoSS0uUchNLcnIT1FIzEsBSuJSVFxZXJKay8PAmpaYU5zKC6W5GRTdXEOcPXRTC_LjU4sLEpNT81JL4p39DA1NjMxMLI1NHY2JUQMA5JwzLw</recordid><startdate>20220401</startdate><enddate>20220401</enddate><creator>GUO JIASHUAI</creator><creator>DENG LIULEI</creator><scope>EVB</scope></search><sort><creationdate>20220401</creationdate><title>In-chip interference test method and in-chip interference test system</title><author>GUO JIASHUAI ; DENG LIULEI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN114264935A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>GUO JIASHUAI</creatorcontrib><creatorcontrib>DENG LIULEI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GUO JIASHUAI</au><au>DENG LIULEI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>In-chip interference test method and in-chip interference test system</title><date>2022-04-01</date><risdate>2022</risdate><abstract>The invention provides a method for testing interference in a chip, which comprises the following steps of: establishing a testing environment, connecting an input end of a first low-noise amplifier to a first end of a first component, and connecting an output end of the first low-noise amplifier to a second detection channel port of a vector network analyzer; the input end of a second low-noise amplifier is connected to a first detection channel port of the vector network analyzer, and the output end of the second low-noise amplifier is connected to the first end of another second component; the signal control output end of the control equipment is connected to the signal control input end of the chip to be tested; power is supplied and work is started; an interference waveform image is obtained, the first low-noise amplifier and the second low-noise amplifier are turned on at the same time through the control equipment, and the S21 parameter waveform is displayed on the vector network analyzer. The embodime</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_CN114264935A
source esp@cenet
subjects MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
title In-chip interference test method and in-chip interference test system
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-06T05%3A20%3A32IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=GUO%20JIASHUAI&rft.date=2022-04-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN114264935A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true