Latency-based instruction reservation in scheduler circuitry in processor

The invention discloses a latency-based instruction reservation cluster in a scheduler circuit in a processor. The scheduler circuit includes a plurality of delay-based reservation circuits, each reservation circuit having an assigned producer instruction cycle delay. The producer instructions with the same periodic latency may be aggregated in the same latency-based reservation circuit. Thus, the number of reservation entries is distributed among a plurality of latency-based reservation circuits to avoid or reduce an increase in the number of scheduling path connections and complexity in each reservation circuit to avoid or reduce an increase in scheduling latency. Scheduling path connections are reduced for a given number of reservation entries on a non-cluster pick circuit because signals (e.g., wake-up signals, pick signals) used to schedule instructions in each delay-based reservation circuit do not have the same clock cycle delay so as not to affect performance. 公开了处理器中的调度器电路中的基于时延的指令预留集群。调度器电路包括多个基于时延的