SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, a semiconductor memory device includes a substrate (20), a source line (SL), a plurality of word lines (WL), a pillar (MP), an outer peripheral conductor layer (62), a lower conductor layer (73), and a first contact (C3L). A source line (SL) is provided above the substrate (20) in the core region (MA). The bottom of the pillar (MP) reaches the source line (SL), and the intersection portions with the plurality of word lines (WL) function as memory cells. The outer peripheral conductor layer (62) is included in the first layer provided with the source line (SL) in the first region (WR), and is provided so as to surround the core region (MA). The lower conductor layer (73) is included in the second layer (D2) in the first region (WR). A first contact (C3L) is provided on the lower conductor layer (73) in the first region (WR) so as to surround the core region (MA), the upper end of the first contact (C3L) being included in the first layer, and the first contact (C3L) being electrical