Integrated circuit mask layout, pattern correction method and mask thereof

The invention discloses a mask layout of an integrated circuit. The mask layout comprises a plurality of active region patterns and a plurality of sealing ring patterns; the active region pattern is parallel to the horizontal direction of the mask layout; an included angle is formed between the sealing ring pattern and the horizontal direction of the mask layout; a plurality of active region patterns form a group, and a plurality of groups of active region patterns are formed in total; each group of active region patterns corresponds to the adjacent alignment mark, and the edge of one side, close to the sealing ring pattern, of each active region pattern in the same group of active region patterns is flush in the vertical direction of the mask layout. Compared with the prior art, the mask layout and the mask manufactured by adopting the layout provided by the invention have the advantage that a better process window can be obtained in the manufacturing process of an integrated circuit. 本发明公开了一种集成电路掩膜版版图，所述掩膜版