INVERTER SYSTEM AND INVERTER SYSTEM CONTROL METHOD

Provided is an inverter system including a level-skip preventing control unit 3 which outputs a gate signal on the basis of a voltage level command V*, the gate signal driving an inverter 4. The level-skip preventing control unit 3 sets a counter C such that, when an output voltage level V of a cert...

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Hauptverfasser: OGAWA RYUICHI, HAMADA SHIZUNORI
Format: Patent
Sprache:chi ; eng
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Zusammenfassung:Provided is an inverter system including a level-skip preventing control unit 3 which outputs a gate signal on the basis of a voltage level command V*, the gate signal driving an inverter 4. The level-skip preventing control unit 3 sets a counter C such that, when an output voltage level V of a certain phase has become UP, the output voltage level V of the phase is prohibited from becoming UP for a predetermined time, and such that, for another phase, an output voltage level V is prohibited from becoming DOWN for a predetermined time. The level-skip preventing control unit 3 also sets a counter C such that, when an output voltage level V of a certain phase has become DOWN, the output voltage level V of the phase is prohibited from becoming DOWN for a predetermined time, and such that, for another phase, an output voltage level V is prohibited from becoming UP for a predetermined time. In this way, in an inverter system having an arbitrary number of phases and an arbitrary number of levels, a level-skip of lin