PROCESS FOR A 3-DIMENSIONAL ARRAY OF HORIZONTAL NOR-TYPE MEMORY STRINGS

In the highly efficient fabrication processes for HNOR arrays provided herein, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities. 在此所提供的一种高效率的水平反或(HNOR)阵列的制造方法中，HNOR阵列中存储晶体管的通道区域从沉积形成之后，直到形成局部字线前的随后沉积电荷捕捉材料的步骤前，均受到一保护层保护。通道区域的硅及保护材料均先以非晶型沉积，而后以一退火步骤进行结晶化。保护材料可以是硼化硅、碳化硅或锗化硅。保护材料可以在通道区域的结晶硅引起较大的晶粒边界，借以提供较大的电荷载子迁移率、较大的导电率及较大的电流密度。