Multi-tap delay circuit and design method thereof

The invention discloses a multi-tap delay circuit and a design method thereof. The multi-tap delay circuit comprises a shunt circuit with N output ends, a combiner circuit with N input ends and N taps, wherein the N input ends of the N taps are respectively connected with the N output ends of the shunt circuit, the N output ends of the N taps are respectively connected with the N input ends of the combiner circuit, and N is a natural number greater than 1. The multi-tap delay circuit also comprises at least one unidirectional conduction device. The input end of at least one tap in the N taps is connected with the corresponding output end of the shunt circuit through a one-way conduction device, and/or the output end of at least one tap in the N taps is connected with the corresponding input end of the combiner circuit through a one-way conduction device. According to the technical scheme, the adverse effect of mutual coupling among multiple taps is avoided, and a basis is provided for the radio frequency self