Chip and wafer packaging method and packaging structure
The invention relates to a chip, a wafer packaging method and a packaging structure, and the chip packaging method comprises the steps: forming a bonding layer on the surface of one or two of a first passivation layer and a second passivation layer after a first solder bump and a second solder bump...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention relates to a chip, a wafer packaging method and a packaging structure, and the chip packaging method comprises the steps: forming a bonding layer on the surface of one or two of a first passivation layer and a second passivation layer after a first solder bump and a second solder bump are formed; cutting the wafer to obtain a chip to be packaged; and enabling the first solder bump to face the second solder bump, and welding the chip and the substrate. In the welding process, the first solder bump and the second solder bump are bonded to form a welding node, and the first passivation layer and the second passivation layer are bonded through the bonding layer; and in the welding process, the first passivation layer and the second passivation layer block the transverse overflow of the welding material, therefore, bridging among different welding nodes caused by overflow of the welding flux is reduced, the reliability of the formed packaging structure is improved, and meanwhile, the process procedur |
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