SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

The present invention improves transistor performance. A semiconductor device according to an embodiment is provided with an insulating film (12) isolating an n-type transistor forming region (Tr1) and a p-type transistor forming region (Tr2) from each other, wherein each of the n-type transistor fo...

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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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description The present invention improves transistor performance. A semiconductor device according to an embodiment is provided with an insulating film (12) isolating an n-type transistor forming region (Tr1) and a p-type transistor forming region (Tr2) from each other, wherein each of the n-type transistor forming region and the p-type transistor forming region is provided with a gate electrode (13) formed in a first direction on a semiconductor substrate (11), and source/drain regions (22) formed on both sides of the gate electrode in a second direction different from the first direction. The distance from an interface between the insulating film and the source/drain regions to an end of the gate electrode in the second direction differs between the n-type transistor forming region and the p-type transistor forming region. 本发明改善了晶体管性能。根据实施例的半导体装置设置有将n型晶体管形成区域(Tr1)和p型晶体管形成区域(Tr2)彼此隔离的绝缘膜(12)，其中，n型晶体管形成区域和p型晶体管形成区域中的每一个都设置有形成在半导体基板(11)上的第一方向上的栅电极(13)以及在栅电极的两侧沿不同于第一方向的第二方向形成的源极/漏极区域(22)。在第二方向上从绝缘膜和源极/漏极区域之间的界面到栅电极的端部的距离在
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN113950741A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN113950741A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN113950741A3</originalsourceid><addsrcrecordid>eNrjZHALdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNR8HUN8fB3UXADivo6-oW6OTqHhAZ5-rkrYNPBw8CalphTnMoLpbkZFN1cQ5w9dFML8uNTiwsSk1PzUkvinf0MDY0tTQ3MTQwdjYlRAwDDoCx4</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>NAGATOMO KOJI</creator><creatorcontrib>NAGATOMO KOJI</creatorcontrib><description>The present invention improves transistor performance. A semiconductor device according to an embodiment is provided with an insulating film (12) isolating an n-type transistor forming region (Tr1) and a p-type transistor forming region (Tr2) from each other, wherein each of the n-type transistor forming region and the p-type transistor forming region is provided with a gate electrode (13) formed in a first direction on a semiconductor substrate (11), and source/drain regions (22) formed on both sides of the gate electrode in a second direction different from the first direction. The distance from an interface between the insulating film and the source/drain regions to an end of the gate electrode in the second direction differs between the n-type transistor forming region and the p-type transistor forming region. 本发明改善了晶体管性能。根据实施例的半导体装置设置有将n型晶体管形成区域(Tr1)和p型晶体管形成区域(Tr2)彼此隔离的绝缘膜(12)，其中，n型晶体管形成区域和p型晶体管形成区域中的每一个都设置有形成在半导体基板(11)上的第一方向上的栅电极(13)以及在栅电极的两侧沿不同于第一方向的第二方向形成的源极/漏极区域(22)。在第二方向上从绝缘膜和源极/漏极区域之间的界面到栅电极的端部的距离在</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220118&amp;DB=EPODOC&amp;CC=CN&amp;NR=113950741A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220118&amp;DB=EPODOC&amp;CC=CN&amp;NR=113950741A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NAGATOMO KOJI</creatorcontrib><title>SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><description>The present invention improves transistor performance. A semiconductor device according to an embodiment is provided with an insulating film (12) isolating an n-type transistor forming region (Tr1) and a p-type transistor forming region (Tr2) from each other, wherein each of the n-type transistor forming region and the p-type transistor forming region is provided with a gate electrode (13) formed in a first direction on a semiconductor substrate (11), and source/drain regions (22) formed on both sides of the gate electrode in a second direction different from the first direction. The distance from an interface between the insulating film and the source/drain regions to an end of the gate electrode in the second direction differs between the n-type transistor forming region and the p-type transistor forming region. 本发明改善了晶体管性能。根据实施例的半导体装置设置有将n型晶体管形成区域(Tr1)和p型晶体管形成区域(Tr2)彼此隔离的绝缘膜(12)，其中，n型晶体管形成区域和p型晶体管形成区域中的每一个都设置有形成在半导体基板(11)上的第一方向上的栅电极(13)以及在栅电极的两侧沿不同于第一方向的第二方向形成的源极/漏极区域(22)。在第二方向上从绝缘膜和源极/漏极区域之间的界面到栅电极的端部的距离在</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHALdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNR8HUN8fB3UXADivo6-oW6OTqHhAZ5-rkrYNPBw8CalphTnMoLpbkZFN1cQ5w9dFML8uNTiwsSk1PzUkvinf0MDY0tTQ3MTQwdjYlRAwDDoCx4</recordid><startdate>20220118</startdate><enddate>20220118</enddate><creator>NAGATOMO KOJI</creator><scope>EVB</scope></search><sort><creationdate>20220118</creationdate><title>SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><author>NAGATOMO KOJI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN113950741A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>NAGATOMO KOJI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NAGATOMO KOJI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><date>2022-01-18</date><risdate>2022</risdate><abstract>The present invention improves transistor performance. A semiconductor device according to an embodiment is provided with an insulating film (12) isolating an n-type transistor forming region (Tr1) and a p-type transistor forming region (Tr2) from each other, wherein each of the n-type transistor forming region and the p-type transistor forming region is provided with a gate electrode (13) formed in a first direction on a semiconductor substrate (11), and source/drain regions (22) formed on both sides of the gate electrode in a second direction different from the first direction. The distance from an interface between the insulating film and the source/drain regions to an end of the gate electrode in the second direction differs between the n-type transistor forming region and the p-type transistor forming region. 本发明改善了晶体管性能。根据实施例的半导体装置设置有将n型晶体管形成区域(Tr1)和p型晶体管形成区域(Tr2)彼此隔离的绝缘膜(12)，其中，n型晶体管形成区域和p型晶体管形成区域中的每一个都设置有形成在半导体基板(11)上的第一方向上的栅电极(13)以及在栅电极的两侧沿不同于第一方向的第二方向形成的源极/漏极区域(22)。在第二方向上从绝缘膜和源极/漏极区域之间的界面到栅电极的端部的距离在</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
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