Middle-section interconnection structure and manufacturing method

The invention relates to a middle-section interconnection structure and a manufacturing method. In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower interlayer dielectric (ILD) layer is disposed over the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from the top of the lower ILD layer. A gate cap layer is disposed on the gate electrode. A top surface of the gate cap layer is aligned or coplanar with a top surface of the lower ILD layer. 本申请涉及中段互连结构及制造方法。在一些实施例中，本公开涉及一种集成电路器件。晶体管结构设置在衬底之上，并且包括一对源极/漏极区域以及在该对源极/漏极区域之间的栅极电极。下部层间电介质(ILD)层设置在该对源极/漏极区域之上并且围绕栅极电极。栅极电极从下部ILD层的顶部凹陷。栅极帽盖层设置在栅极电极上。栅极帽盖层的顶表面与下部ILD层的顶表面对准或共面。