Method and circuit for solving slow response of feedback loop of linear voltage regulator

The invention discloses a method for solving slow response of a feedback loop of a linear voltage regulator. The method comprises the following steps: S1, enabling a circuit to start to work to increase a VREF voltage value; S2, forming a delay network by using a resistor R1 and a capacitor C1, and enabling the VREF voltage to be higher than the VF1 voltage; and enabling a comparator COMP to output a high level, turning on a controllable bias current NMOS tube, and enabling the current to charge the VFB, so as to raise the VFB; S3, when the voltage of the VF1 is higher than the voltage of the VREF-0.2 V, outputting a low level by using the comparator COMP, and closing the controllable bias current NMOS tube; and S4, enabling the VFB to rise through a resistor Rf2 and a capacitor Cc network until the VFB is equal to the VREF value. When the circuit works, the VFB rises quickly and is not restrained by static power consumption and external compensation capacitance; after the controllable bias current is closed,