Flow convergence during hardware-software design for heterogeneous and programmable devices

For an application having a software portion for implementation in a data processing engine (DPE) array of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation flow is performed, using a processor executing a hardware compiler, on the hardware portion based on an interface block solution that maps logical resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to not meeting a design metric during the implementation flow, an interface block constraint is provided from the hardware compiler to a DPE compiler. In response to receiving the interface block constraint, an updated interface block solution is generated, using the processor executing the DPE compiler, and provided from the DPE compiler to the hardware compiler. 对于具有用于在设备的数据处理引擎阵列(DPE)中实现的软件部分和用于在所述设备的可编程逻辑(PL)中实现的硬件部分的应用，基于接口块方案，通过使用执行硬件编译器的处理器在所述硬件部分上执行实施流程，所述接口块方案将所述软件部分使用的逻辑资源映射到将所述DPE阵列耦接到所述PL的接口块的硬件。响应于在所述实施流程中不满足设计指标，从所述硬件编译器