HARDWARE-SOFTWARE DESIGN FLOW FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES

For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array. 对于指定了以下项的应用：用于在设备的数据处理引擎(DPE)阵列内实现的软件部分、和用于在设备的可编程逻辑(PL)内实现的硬件部分，生成应用的逻辑架构和第一接口解决方案，该第一接口解决方案指定逻辑资源到DPE阵列与可编程逻辑之间的接口电路块的硬件的映射。基于逻辑架构和第一接口解决方案构建硬件部分的框图。在框图上执行实现流程。编译应用的软件部分以在DPE阵列的一个或多个DPE中实现。