EFFICIENT REDISTRIBUTION LAYER TOPOLOGY

The subject of the invention is efficient redistribution layer topology. In some examples, a chip scale package (CSP) (106) comprises a semiconductor die (108) ; a passivation layer (209) abutting the semiconductor die; a via (210) extending through the passivation layer; and a first metal layer (218) abutting the via. The CSP also includes an insulation layer (216) abutting the first metal layer, with the insulation layer having an orifice (217) with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer (224) abutting the insulation layer and adapted to couple to a solder ball. The second metal layer (224) abuts the first metal layer at a point of contact defined by the orifice in the insulation layer. 本申请题为"高效重分布层拓扑结构"。在一些示例中，芯片级封装(CSP)(106)包括半导体管芯(108)；邻接半导体管芯的钝化层(209)；延伸通过钝化层的通孔(210)；和邻接通孔的第一金属层(218)。CSP还包括邻接第一金属层的绝缘层(216)，其中绝缘层具有小于32400平方微米的最大水平面积的孔口(217)。CSP进一步包括邻接绝缘层并适于耦合到焊球(112)的第二金属层(224)。第二金属层在由绝缘层中的孔口限定的接触点处邻接第一金属层。