Method and a circuit for measuring time sequence unit retention time

The invention provides a method and a circuit for measuring time sequence unit retention time. The method is suitable for a time sequence unit retention time measurement circuit, and the circuit comprises a clock signal generation module, a first selection module, a second selection module, a delay detection module, a first clock phase controller, a second clock phase controller, a data signal transmission module, a clock signal transmission module, a time sequence unit to be measured and a control module. The method comprises the following steps: respectively determining a first period value, a second period value and a third period value of a clock signal, the first period value being a critical period of the clock signal when a time sequence unit to be tested correctly receives in a first test path, the second period value being a critical period of the clock signal when a delay detection module correctly receives in a second test path, the third period value being a critical period of the clock signal whe