Configurable accurate delay circuit structure for high-speed ADC (Analog to Digital Converter)

The invention discloses a configurable accurate delay circuit structure for a high-speed ADC, and belongs to the field of electronic circuits, the configurable accurate delay circuit structure comprises a PMOS tube P1, an NMOS tube N1 and a capacitor CL, the gate end of the PMOS tube P1 and the gate end of the NMOS tube N1 are jointly connected with an input voltage Vin, the drain end of the PMOS tube P1 and the drain end of the NMOS tube N1 are jointly connected with an output voltage Vout, one end of the capacitor CL is connected with the output voltage Vout, and the other end of the capacitor CL is grounded; the circuit further comprises a resistor R1, a resistor R2 and a plurality of capacitors, the resistor R1 is connected to the drain end of the PMOS tube P1 in series, and the resistor R2 is connected to the drain end of the NMOS tube N1 in series. The plurality of capacitors are connected in parallel between the capacitor CL and the output voltage Vout, and each capacitor connected in parallel between