Accurate delay circuit structure for high-speed analog-to-digital converter

The invention discloses an accurate delay circuit structure for a high-speed analog-to-digital converter, which belongs to the field of integrated circuits and comprises an NMOS (N-channel Metal Oxide Semiconductor) tube Q1 and a PMOS (P-channel Metal Oxide Semiconductor) tube Q2, and a high-precision resistor R1 and a high-precision resistor R2 are connected in series between the drain end of the NMOS tube Q1 and the drain end of the PMOS tube Q2. The resistance values of the resistor R1 and the resistor R2 are far greater than the on resistance Ron of the MOS tube. The pull-up network and the pull-down network are respectively provided with a high-precision resistor to control and calculate the time delay of each stage of phase inverter, so that the time delay of each stage of phase inverter is not mainly controlled by the on resistance of an NMOS (N-channel Metal Oxide Semiconductor) tube or a PMOS (P-channel Metal Oxide Semiconductor) tube, but is determined by the introduced resistor and load capacitance