Micro-bump chip packaging structure with stress buffering effect and preparation method thereof

The invention discloses a micro-bump chip packaging structure with a stress buffering effect and a preparation method thereof. The micro-bump chip packaging structure comprises: a semiconductor substrate; a welding pad arranged on the semiconductor substrate; a passivation layer located on the surfaces of the semiconductor substrate and the bonding pad and provided with a window, wherein the window corresponds to the bonding pad and is smaller than the bonding pad in size; a seed layer which is located on the bonding pad and extends to a part of the surface of the passivation layer towards the periphery; a micro bump structure which is located on the seed layer and comprises a metal column and a micro bump located at the top part of the metal column; and a buffer dielectric layer is arranged on the passivation layer around the micro bump structure, and the buffer dielectric layer is tightly connected with the micro bump structure. According to the micro-bump chip packaging structure, the buffer dielectric lay