Multi-chip package and manufacture method thereof

A multi-chip package and a manufacturing method thereof are disclosed. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via which penetrates through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via. 本发明公开一种多芯片封装件及其制造方法。多芯片封装件包括：中介层，包括介电主体、被所述介电主体隔开的多个半导体主体、贯穿所述介电主体的贯穿通路以及位于所述多个半导体主体中的每一者中的布线结构；多个半导体芯片，并排地位于所述中介层的第一表面上且电连接至所述布线结构；包封体，位于所述中介层的所述第一表面上且包封所述