Integrated chip
Some embodiments of the invention relate to an integrated chip comprising: an underside interconnect dielectric layer disposed on a substrate; the interconnect circuit disposed on the underside interconnect dielectric layer; a first interconnect dielectric layer disposed around the outer sidewall of...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | Some embodiments of the invention relate to an integrated chip comprising: an underside interconnect dielectric layer disposed on a substrate; the interconnect circuit disposed on the underside interconnect dielectric layer; a first interconnect dielectric layer disposed around the outer sidewall of the interconnect circuit; the graphene-containing protective liner layer that is directly disposed on the outer sidewall of the interconnect circuit and the upper surface of the interconnect circuit. The integrated chip also includes: a first etch stop layer directly disposed on an upper surface of the first interconnect dielectric layer; and a second interconnect dielectric layer disposed on the first interconnect dielectric layer and the interconnect circuit. In addition, an interconnect via extends through the second interconnect dielectric layer, is directly disposed on the protective liner layer, and is electrically coupled to the interconnect circuit.
本发明一些实施例关于集成芯片,其包括下侧内连线介电层,配置于基板上。内连线线路,配置于下侧内连线介电层上;以及第一 |
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