Method for integrated RTL description with HDL for digital circuit design
The present invention relates to a method for integrated register level (RTL) description in hardware description language (HDL) for digital circuit design, the method using at least one synthesis engine. 本发明涉及一种用于数字电路设计的综合用硬件描述语言(HDL)的寄存器级(RTL)描述的方法，该方法使用至少一个综合引擎。...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | chi ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Zusammenfassung: | The present invention relates to a method for integrated register level (RTL) description in hardware description language (HDL) for digital circuit design, the method using at least one synthesis engine.
本发明涉及一种用于数字电路设计的综合用硬件描述语言(HDL)的寄存器级(RTL)描述的方法，该方法使用至少一个综合引擎。 |
|---|