Weighted summation circuit based on fractional order memristor array and use method thereof

The invention relates to a weighted summation circuit based on a fractional order memristor array and a use method thereof According to the technical scheme, a terminal Aij in the ith row and the jth column is connected with a terminal RM2 of a fractional order memristor (102) in the ith row and the jth column, wherein i is larger than or equal to 1 and smaller than or equal to M, and j is greater than or equal to 1 and less than or equal to N), and an order control signal Uij of the ith row and the jth column is added between a terminal Aij of the ith row and the jth column and GND so as to adjust the order of the fractional order memristor (102); a voltage input signal terminal ri in the ith row is respectively connected with terminals RM0 of the N fractional order memristors (102) in the ith row; the voltage input signal terminal cj of the jth column is correspondingly connected with the terminal RM1 of the M fractional order memristors (102) of the jth column and the input end Ij of the jth current sampli