SEMICONDUCTOR SUBSTRATE ARRANGEMENT

A semiconductor substrate arrangement comprises a semiconductor substrate (10) comprising a dielectric insulation layer (11) and a first metallization layer (111) attached to the dielectric insulation layer (11), wherein the first metallization layer (111) is arranged on the dielectric insulation layer (11) in a vertical direction (z). The semiconductor substrate arrangement further comprises an electrically conductive coating (20) arranged on the first metallization layer (111) in the vertical direction (z) such that the first metallization layer (111) is arranged between the electrically conductive coating (20) and the dielectric insulation layer (11). In in a horizontal plane (x-y) within a first distance (x1) from the outer perimeter of the electrically conductive coating (20), the first metallization layer (111) does not comprise any cavities or trenches (40), or only cavities or trenches (40) having a maximum width (w40) in a horizontal direction (x, y) that is less than 10 [mu]m and a maximum depth (d4