Clock data recovery circuit, memory storage device and signal generation method

The invention provides a clock data recovery circuit. The clock data recovery circuit comprises a phase detection circuit, a first voting circuit, a low-pass filter circuit and a phase interpolation circuit, the phase detection circuit is used for receiving a first signal and a clock signal and generating a phase signal. The first voting circuit is used for charging at least one capacitor part according to the phase signal and generating a first voting signal according to a charging result. The low-pass filter circuit is used for generating a phase control signal according to the first voting signal. The phase interpolation circuit is configured to generate the clock signal according to the phase control signal. In addition, the invention also provides a memory storage device and a signal generation method. 本发明提供一种时钟数据回复电路，其包括相位检测电路、第一投票电路、低通滤波电路及相位内插电路。所述相位检测电路用以接收第一信号与时钟信号并产生相位信号。所述第一投票电路用以根据所述相位信号对至少一电容元件进行充电并根据充电结果产生第一投票信号。所述低通滤波电路用以根据所述第一投票信号产生相位控制信号。所述相位内插电路用以根据所述相位控制信号产生所述时钟信号。此外，本发明也提供一种存储器存储装置及信号产生方法