MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. The first data line is electrically coupled to a first channel region of a first transistor. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to a second channel region of a second transistor, the second channel region electrically coupled to the charge storage structure and being between a charge storage structure of the first transistor and the third data line. The first access line is located on a first level of the apparatus. The second access line is located on a second level of the apparatus. The charge storage structure is located on a level of the apparatus between the first and second levels. 一些实施例包含设备和形成所述设备的方法。所述设备中的一个包含存储器单元、第一、第二和第三数据线及第一和第二存取线。所述第一数据线电耦合到第一晶体管的第一沟道区。所述第二数据线电耦合到所述第一沟道区。所述第三数据线电耦合到第二晶体管的第二沟道区，所述第二沟道区电耦合到电荷存储结构且在所述第一晶体管的电