Dipole design high-k gate dielectric and method of forming same

The invention relates to a dipole design high-K gate dielectric and a method of forming the same. The method includes forming an oxide layer on a first semiconductor region, and depositing a first high-k dielectric layer over the oxide layer. The first high-k dielectric layer is formed of a first high-k dielectric material. The method further includes depositing a second high-k dielectric layer over the first high-k dielectric layer, where the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material, depositing a dipole film over and in contact with a layer selected from the first high-k dielectric layer and the second high-k dielectric layer, an annealing process is performed to drive dipole dopants in the dipole film into the layer, the dipole film is removed, and a gate electrode is formed over the second high-k dielectric layer. 本公开涉及偶极设计高K栅极电介质及其形成方法。一种方法，包括：在第一半导体区域上形成氧化物层，以及在氧化物层之上沉积第一高k电介质层。第一高k电介质层由第一高k电介质材料形成。该方法还包括在第一高k电介质层之