Integrated circuit die, three-dimensional integrated circuit stack, and method of forming integrated circuit
In some embodiments, the present disclosure relates to a three-dimensional integrated circuit (IC) stack including a first integrated circuit die bonded to a second integrated circuit die. The first integrated circuit die includes a first semiconductor substrate, a first interconnect structure dispo...
Gespeichert in:
Hauptverfasser: | , , , , , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | CHEN PINZI LIN XINGZHI ZHU YIXIN CHEN ZHEWEI YANG DUNNIAN GAO MINFENG LIU RENCHENG |
description | In some embodiments, the present disclosure relates to a three-dimensional integrated circuit (IC) stack including a first integrated circuit die bonded to a second integrated circuit die. The first integrated circuit die includes a first semiconductor substrate, a first interconnect structure disposed on a front side of the first semiconductor substrate, and a first bonding structure disposed over the first interconnect structure. The second integrated circuit die includes a second semiconductor substrate, a second interconnect structure disposed on a front side of the second semiconductor substrate, and a second bonding structure disposed on a back side of the second semiconductor substrate. The first engagement structure faces the second engagement structure. In addition, the three-dimensional integrated circuit stack includes a first backside contact extending from the second bonding structure to a backside of the second semiconductor substrate and thermally coupled to at least one of the first interconne |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN113257796A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN113257796A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN113257796A3</originalsourceid><addsrcrecordid>eNqNyqEOwjAQANAaBAH-4fCbGAssSLJAwKDwy6W9bhfa69Ie_4_BgUA985Ym3ERpzKjkwHK2L1ZwTBXolIlqx5GkcBIMwN-zKNpnBSgOIumUHCQPPuXIMv74a7PwGAptPq7M9nJ-9Nea5jRQmdGSkA79vWna3b7rjodT-895AzjPQgY</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Integrated circuit die, three-dimensional integrated circuit stack, and method of forming integrated circuit</title><source>esp@cenet</source><creator>CHEN PINZI ; LIN XINGZHI ; ZHU YIXIN ; CHEN ZHEWEI ; YANG DUNNIAN ; GAO MINFENG ; LIU RENCHENG</creator><creatorcontrib>CHEN PINZI ; LIN XINGZHI ; ZHU YIXIN ; CHEN ZHEWEI ; YANG DUNNIAN ; GAO MINFENG ; LIU RENCHENG</creatorcontrib><description>In some embodiments, the present disclosure relates to a three-dimensional integrated circuit (IC) stack including a first integrated circuit die bonded to a second integrated circuit die. The first integrated circuit die includes a first semiconductor substrate, a first interconnect structure disposed on a front side of the first semiconductor substrate, and a first bonding structure disposed over the first interconnect structure. The second integrated circuit die includes a second semiconductor substrate, a second interconnect structure disposed on a front side of the second semiconductor substrate, and a second bonding structure disposed on a back side of the second semiconductor substrate. The first engagement structure faces the second engagement structure. In addition, the three-dimensional integrated circuit stack includes a first backside contact extending from the second bonding structure to a backside of the second semiconductor substrate and thermally coupled to at least one of the first interconne</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210813&DB=EPODOC&CC=CN&NR=113257796A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210813&DB=EPODOC&CC=CN&NR=113257796A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHEN PINZI</creatorcontrib><creatorcontrib>LIN XINGZHI</creatorcontrib><creatorcontrib>ZHU YIXIN</creatorcontrib><creatorcontrib>CHEN ZHEWEI</creatorcontrib><creatorcontrib>YANG DUNNIAN</creatorcontrib><creatorcontrib>GAO MINFENG</creatorcontrib><creatorcontrib>LIU RENCHENG</creatorcontrib><title>Integrated circuit die, three-dimensional integrated circuit stack, and method of forming integrated circuit</title><description>In some embodiments, the present disclosure relates to a three-dimensional integrated circuit (IC) stack including a first integrated circuit die bonded to a second integrated circuit die. The first integrated circuit die includes a first semiconductor substrate, a first interconnect structure disposed on a front side of the first semiconductor substrate, and a first bonding structure disposed over the first interconnect structure. The second integrated circuit die includes a second semiconductor substrate, a second interconnect structure disposed on a front side of the second semiconductor substrate, and a second bonding structure disposed on a back side of the second semiconductor substrate. The first engagement structure faces the second engagement structure. In addition, the three-dimensional integrated circuit stack includes a first backside contact extending from the second bonding structure to a backside of the second semiconductor substrate and thermally coupled to at least one of the first interconne</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyqEOwjAQANAaBAH-4fCbGAssSLJAwKDwy6W9bhfa69Ie_4_BgUA985Ym3ERpzKjkwHK2L1ZwTBXolIlqx5GkcBIMwN-zKNpnBSgOIumUHCQPPuXIMv74a7PwGAptPq7M9nJ-9Nea5jRQmdGSkA79vWna3b7rjodT-895AzjPQgY</recordid><startdate>20210813</startdate><enddate>20210813</enddate><creator>CHEN PINZI</creator><creator>LIN XINGZHI</creator><creator>ZHU YIXIN</creator><creator>CHEN ZHEWEI</creator><creator>YANG DUNNIAN</creator><creator>GAO MINFENG</creator><creator>LIU RENCHENG</creator><scope>EVB</scope></search><sort><creationdate>20210813</creationdate><title>Integrated circuit die, three-dimensional integrated circuit stack, and method of forming integrated circuit</title><author>CHEN PINZI ; LIN XINGZHI ; ZHU YIXIN ; CHEN ZHEWEI ; YANG DUNNIAN ; GAO MINFENG ; LIU RENCHENG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN113257796A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHEN PINZI</creatorcontrib><creatorcontrib>LIN XINGZHI</creatorcontrib><creatorcontrib>ZHU YIXIN</creatorcontrib><creatorcontrib>CHEN ZHEWEI</creatorcontrib><creatorcontrib>YANG DUNNIAN</creatorcontrib><creatorcontrib>GAO MINFENG</creatorcontrib><creatorcontrib>LIU RENCHENG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHEN PINZI</au><au>LIN XINGZHI</au><au>ZHU YIXIN</au><au>CHEN ZHEWEI</au><au>YANG DUNNIAN</au><au>GAO MINFENG</au><au>LIU RENCHENG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit die, three-dimensional integrated circuit stack, and method of forming integrated circuit</title><date>2021-08-13</date><risdate>2021</risdate><abstract>In some embodiments, the present disclosure relates to a three-dimensional integrated circuit (IC) stack including a first integrated circuit die bonded to a second integrated circuit die. The first integrated circuit die includes a first semiconductor substrate, a first interconnect structure disposed on a front side of the first semiconductor substrate, and a first bonding structure disposed over the first interconnect structure. The second integrated circuit die includes a second semiconductor substrate, a second interconnect structure disposed on a front side of the second semiconductor substrate, and a second bonding structure disposed on a back side of the second semiconductor substrate. The first engagement structure faces the second engagement structure. In addition, the three-dimensional integrated circuit stack includes a first backside contact extending from the second bonding structure to a backside of the second semiconductor substrate and thermally coupled to at least one of the first interconne</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | chi ; eng |
recordid | cdi_epo_espacenet_CN113257796A |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Integrated circuit die, three-dimensional integrated circuit stack, and method of forming integrated circuit |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-12T02%3A00%3A10IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHEN%20PINZI&rft.date=2021-08-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN113257796A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |