Integrated circuit die, three-dimensional integrated circuit stack, and method of forming integrated circuit
In some embodiments, the present disclosure relates to a three-dimensional integrated circuit (IC) stack including a first integrated circuit die bonded to a second integrated circuit die. The first integrated circuit die includes a first semiconductor substrate, a first interconnect structure dispo...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | In some embodiments, the present disclosure relates to a three-dimensional integrated circuit (IC) stack including a first integrated circuit die bonded to a second integrated circuit die. The first integrated circuit die includes a first semiconductor substrate, a first interconnect structure disposed on a front side of the first semiconductor substrate, and a first bonding structure disposed over the first interconnect structure. The second integrated circuit die includes a second semiconductor substrate, a second interconnect structure disposed on a front side of the second semiconductor substrate, and a second bonding structure disposed on a back side of the second semiconductor substrate. The first engagement structure faces the second engagement structure. In addition, the three-dimensional integrated circuit stack includes a first backside contact extending from the second bonding structure to a backside of the second semiconductor substrate and thermally coupled to at least one of the first interconne |
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