Common-mode voltage suppression PWM strategy with minimum switching loss
The invention discloses a common-mode voltage suppression PWM strategy with minimum switching loss. The common-mode voltage suppression PWM strategy is implemented by generating driving signals Sa, Sb and Sc of a three-phase two-level frequency converter by using a PWM modulator on a three-phase vol...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention discloses a common-mode voltage suppression PWM strategy with minimum switching loss. The common-mode voltage suppression PWM strategy is implemented by generating driving signals Sa, Sb and Sc of a three-phase two-level frequency converter by using a PWM modulator on a three-phase voltage source inverter. According to the common-mode voltage suppression PWM strategy, the minimum switching loss is achieved within the full power factor range, the system efficiency is improved, and the common-mode voltage can be effectively suppressed.
本发明公开了具备最小开关损耗的共模电压抑制PWM策略,包括在三相电压源逆变器上使用PWM调制器,生成三相两电平变频器的驱动信号Sa,Sb和Sc。本发明的共模电压抑制PWM策略,在全功率因数范围内实现最小开关损耗,提高了系统效率,能够有效地抑制共模电压。 |
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