MANAGING SUB-BLOCK ERASE OPERATIONS IN MEMORY SUB-SYSTEM

The present invention relates to managing the sub-block erase operations in a memory sub-system. A processing device in a memory system receives an erase request to erase the data stored at a data block of a memory device, the erase request identifies a selected sub-block of a plurality of sub-blocks of the data block for erase, and each of the plurality of sub-blocks comprises selection gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, and each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline by an amount equal to a step down interval. 本申请案涉及在存储器子系统中管理子块擦除操作。存储器系